1. Field of the Invention
The present invention relates to a signal processing system and a method of the same. More particularly, it relates to a signal processing system having a linear equalizer, an intersymbol-interference cancelling means, and a discriminator, which can be applied to, for example, a digital data reproduction system such as a digital video-signal recording and reproducing apparatus (VTR), and a method of the same.
2. Description of the Related Art
In digital VTRs or other digital magnetic recording and reproducing apparatuses, digital data is converted to analog data and recorded on a magnetic recording medium such as a magnetic tape by a magnetic head. When reproducing the digital data, the source analog data is detected from the magnetic recording medium and equalized by a filter known as a reproduction equalizer to shape its waveform and minimize the intersymbol-interference (ISI). As such a reproduction equalizer, mention may be made of analog filter comprised of a coil (L) or capacitor (C), a transversal filter comprised of a plurality of series connected delay lines, each of which delays a signal by a predetermined unit time, connected in series, and a plurality of coefficient multipliers, or other linear equalizers (LE). The analog data linearly equalized by the linear equalizer is applied to a discriminator. There, the equalized data is compared with threshold data, thereby reproducing the original digital data before recorded on the magnetic recording medium.
When using a linear equalizer as a reproduction equalizer, however, the linear equalizer operates to match the desired frequency characteristics without separating the effective signal component and noise component included in the analog signal, so it suffers from the disadvantage that the noise component is emphasized too much. To overcome this disadvantage, a trade-off is necessary between the frequency characteristics of the reproduction equalization circuit and the S/N. Adjustment is necessary to minimize the error rate of the final digital data reproduced. The following methods have been employed for this adjustment.
In a first method, a Viterbi decoder is employed as the reproduction equalizer. Due to the use of a Viterbi decoder, maximum use of the S/N of the analog reproduction signal is possible before the discrimination. This method is known by, for example, Eto et al. "Digital Video Recording Technology", Nikkan Kogyo Shimbunsha, pp. 72-84. Details will be given below.
In a Viterbi decoder, n number of states at a certain point of time separated by values of the ISI determined in advance are defined by a combination of n bits of data discriminated prior to that time. Each time one bit worth of processing is completed, the n number of states are updated to the next n number of states. There is a history to the n number of states and an estimated sequence of likelihood of the previous discriminated values. Assuming the noise has a Gaussian distribution, the estimated likelihood of the n number of states is determined by the sum up to then of the squares of the difference between the values of the reproduced signals assuming no noise (target values) and the values of the actually reproduced signals. Also, based on the assumption that the n number of states are defined from those of all the possible previous states having the greatest estimated likelihood, the previous states are updated to the next states and the history and estimated sequence of likelihood of the discrimination values are also updated. If the most likely states are repeatedly changed in this way, at a certain stage, the history up to several bits before that stage will converge and the discriminated values up to then will be conclusively decided. In this method, the discrimination is performed making maximum effective use of the signal power of the reproduced data, and thus digital data having an extremely low error rate is obtained compared with the usual threshold discrimination. Since this Viterbi decoding method requires one to calculate the above-mentioned total sum of the squares, the size of the circuit to calculate the same becomes larger. In addition, there is still the major disadvantage that it is difficult to carry out the decoding by the clock of the data rate at a high speed, so a multistate Viterbi decoder has not been used in digital VTRs etc.
The simplest example of use of a Viterbi decoder is the application to NRZI signal processing. If recording and reproducing in an NRZI signal processing system and equalizing so that the unit pulse is given a value between (1, -1), the number of states can be expressed by two values. There is no longer a need for calculation of the total sum of squares, therefore it is possible to construct the Viterbi decoder simply. Further, if a partial response class IV (PR-IV) signal processing method is employed so that data is recorded on the recording medium by precoding of a 2-bit delay and (mod2) addition, the data is then reproduced, and the reproduced data is equalized so that the unit pulse is given, a value among (1, 0, -1), the resultant data becomes data by the NRZI signal processing method if viewing every other bit. Therefore, two parallel simple NRZI Viterbi decoders may be employed and operated at a speed half the data rate. The combination of this PR IV method and the Viterbi decoders enables construction of a Viterbi decoder practical in terms of both the circuit size and operating speed. Therefore, this is becoming the general practice in recent digital VTRs.
Below, a PR IV Viterbi decoder will be also referred to as a "VD". In the VD explained above, assuming there is no correlation in the noise and the noise has Gaussian distribution, theoretically the S/N may be improved by 3 dB compared with threshold discrimination. However, noise is given correlation by passing through the linear equalizer. Also, it is difficult to perform equalization in practice according to the PR IV standard. Therefore, it is still not possible to realize the improvement expected with a Viterbi decoder.
Below, as a second method, an explanation will be made of the use of a nonlinear equalizer as a reproduction equalizer. In the second method, the intersymbol-interference (ISI) can be suppressed by using a linear canceler (LC) or a nonlinear canceler (NLC) or other nonlinear equalizer, without emphasizing the noise. Namely, in this method, copies of the ISI determined by the combination of the provisionally discriminated values of the bits of data preceding and succeeding a certain time are set in advance, are subtracted from the output data of the linear equalizer, and then are once again discriminated to reproduce the digital data. A linear canceler is effective only with regard to linear distortion, while a nonlinear canceler wherein copies of the ISI are used is effective with respect to nonlinear distortion as well. There are known various methods of constructing a reproduction equalizer using an NLC, but a table lookup type nonlinear canceler (NLC) enables full consideration to be given to the length of the ISI caused by the equalization error and further is simple in circuit construction.
A table lookup type NLC uses as a lookup table a random access memory (RAM) such as a dynamic RAM, or a static RAM, in which the ISI data is stored in advance, converts the combination of the discriminated values of several bits of data preceding and succeeding a certain time, which are discriminated by a first threshold discriminator based on the output data of the linear equalizer, to an address for the lookup table, reads out the value of the ISI from the lookup table at the address, subtracts the read data from the equalized data, which may be delayed by a predetermined time for adjusting the timing of the equalized data and the address generation, and performs discrimination again by a second threshold discriminator to obtain the digital data.
A reproduction equalizer in which a table lookup type NLC is employed will be described in more detail with reference to FIG. 1.
FIG. 1 is a view showing the construction of an example of a reproduction equalizer 7. The reproduction equalizer 7 includes a linear equalizer 11, a first binary discriminator 12, a first delay line 13 comprised of 2n unit time delaying elements connected in series, an ISI lookup table 14, a second delay line 15 consisting of n unit time delaying elements connected in series, a subtractor 16, and a second binary discriminator 17. The first binary discriminator 12, the first delay line 13, the ISI lookup table 14, the second delay line 15, and the subtractor 16 form a table lookup type nonlinear equalizer (NLC). The linear equalizer 11 linearly equalizes a waveform of an input signal such as analog source data read from a magnetic tape in a digital VTR, to provide linearly equalized analog data X[k], where k indicates a current time at which the input signal is obtained. The linearly equalized data X[k] is provisionally discriminated at the binary discriminator 12 to provide provisional discrimination data A[k] of (0 or 1), and also delayed by n unit times at the second delay line 15 to provide linearly equalized and delayed data X[k'], where k' indicates a time different from the current time k by the n unit times, i.e., k'=k-n. The ISI lookup table 14 stores copies of ISI data ISI {A} which are previously determined when the source analog data does not include noise. The provisional discrimination data A[k] is applied to the first delay line 13 and consecutively delayed thereat to output address components A[k] to A[k-2n] each of which consists of one bit and which are applied to the address terminals a.sub.1 to a.sub.2n of the ISI lookup table 14. Art address {A} consists of the address components A[k] to A[k-2n] and is used to read corresponding ISI data ISI{A} from the ISI lookup table
The subtractor 16 subtracts the ISI data ISI{A} read from the ISI lookup table 14 from the linearly equalized and delayed analog data X[k'] to provide analog data Y [k'] free of ISI. The ISI free analog data Y[k'] is applied to the second discriminator 17 to provide a discriminated result (final discrimination data) A' [k'] of "1" or "0". In the table lookup type NLR, the first binary discriminator 12 and the first delay line 13 function as a means for generating the address {A}, and the second delay line 15 functions as a timing adjustment means for adjusting the time of the linearly equalized analog data X[k] to the ISI data ISI{A}.
Table 1 shows nomenclatures of the above signals.
TABLE 1 ______________________________________ Symbols Meanings ______________________________________ k current time k' delay time delayed from k by -n unit times k' = k - n {A} address of 2n bits {A} = A[k] + A[k - 1] . . . + A[k - 2n] X[k] linearly equalized data X[k'] linearly equalized and delayed data A[k] provisional discrimination data of (0,1) ISI{A} intersymbol-interference(ISI) data of address {A} Y[k'] ISI free analog data A'[k'] final discrimination data ______________________________________
The provisional discrimination data A{k} (A{k}=1 or 0) provisionally discriminated by the first binary discriminator 12 based on the equalized signal X[k] linearly equalized at the linear equalizer 11 becomes the address {A} of the lookup table 14 by the 2n-stage delay line 13. The address {A} is comprised of 2n bits and is determined by the 2n number of provisional discrimination data A{i}, that is, the (2n+1) number of provisional discrimination data A{i} (i=k, k-1, . . . , k-2n) of the results of the discrimination of the linearly equalized data X[k] before subtraction of the ISI, from which the provisional discrimination data A[k'] (where k'=k-n) is removed. To eliminate the ISI caused by the combination of the n bits of data preceding and succeeding the time k of the provisional discrimination data, a RAM (not shown) forming the lookup table 14 has to have a capacity enabling storage of 2.sup.2n bits of ISI data. The ISI data ISI{A} of the address {A} read from the lookup table 14 is subtracted from the linearly equalized and delayed data X[k'] output from the n-stage delay line 15 in the computation circuit (subtractor) 16 to produce the ISI free data Y[k']. This data X[k'] is discriminated by the second binary discriminator 17 and the resultant discrimination data A'[k'] is used as the final discrimination data.
In the reproduction equalizer 7, the RAM is used for the lookup table 14, so the circuit construction is extremely simple and it is possible to easily realize an NLC which can eliminate the ISI data ISI{A} when ISI data of sufficiently long preceding and succeeding bits is considered. However, since it is necessary to store in advance into the RAM the ISI data to be adjusted, which increases by the 2n power of 2(2.sup.2n), when considering the preceding and succeeding five bits, it is necessary to adjust and set 1024 types of ISI data to the lookup table 14. Tremendous work is involved in adjusting the bits of the ISI data. Therefore, in practice, the limit is about 16 combinations for the two preceding bits and two succeeding bits. Full utilization therefore could not be made of the merits of the circuit construction of the reproduction equalizer 7.
Further, in both of the linear canceler and the nonlinear canceler contained in the reproduction equalizer 7, it is a prerequisite that there be little error included in the provisional discrimination data since suitable ISI data ISI{A} is subtracted from the linearly equalized and delayed data X[k']. Error is inevitably included in the provisional discrimination data A[k]. Under actual conditions, the expected effect of improvement by the nonlinear canceler cannot be achieved. There is still the disadvantage of propagation of error.
In summary, in the reproduction equalization method, a linear equalizer, Viterbi decoder (VD), or nonlinear canceler is employed, as a reproduction equalizer, but, as mentioned above, when a linear canceler is used, since the linear equalizer tries to match the desired frequency characteristics without separation between the effective signal component and the noise component contained in the analog signal, there is the disadvantage that the noise is emphasized. Further, there is the disadvantage that a trade off is necessary between the frequency characteristics of the reproduction equalization circuit and the S/N and adjustment is required to minimize the error rate of the final digital (discrimination) data. Also, as mentioned above, in the method of reproduction equalization using a Viterbi decoder as the reproduction equalizer, since the noise is given correlation by passing through the linear equalizer, it is difficult to equalize in practice by the PR-IV standard. Therefore, there is also the disadvantage that it is not possible to realize the improvement expected with a Viterbi decoder. Further, as mentioned above, in the method of reproduction equalization using a nonlinear canceler as the reproduction equalizer, it is necessary to store in advance into the RAM used as the lookup table many bits of ISI data. The ISI data to be adjusted increases by the 2n power of 2(2.sup.2n), so when considering the preceding five and succeeding five bits, for example, it is necessary to adjust and set 1024 types of ISI data. Tremendous work is involved in adjusting each type of ISI data. Therefore, in practice the limit is about 16 types for the two preceding bits and the two succeeding bits. There is further the disadvantage that full utilization cannot be made of the merits of the circuit construction. Further, in both of the linear canceler and the nonlinear canceler, it is a prerequisite that there be little error included in the provisional discrimination data since suitable ISI data is subtracted from the linearly equalized and delayed reproduction signal. Error is inevitably included in the provisional discrimination data, and then, under actual conditions, the effect of improvement by the nonlinear canceler is deteriorated and it further suffers form the disadvantage of propagation of error.